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PRELIMINARY DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD25UC8AAFA-6B (32M words x 64 bits, 1 Rank)
Description
The EBD25UC8AAFA-6B is 32M words x 64 bits, 1 rank Double Data Rate (DDR) SDRAM unbuffered module, mounting 8 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 184-pin socket type dual in line memory module (DIMM) PCB height: 31.75mm Lead pitch: 1.27mm * 2.5V power supply * Data rate: 333Mbps (max.) * 2.5 V (SSTL_2 compatible) I/O * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data inputs and outputs are synchronized with DQS * 4 internal banks for concurrent operation (Component) * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data referenced to both edges of DQS * Auto precharge option for each burst access * Programmable burst length: 2, 4, 8 * Programmable /CAS latency (CL): 2, 2.5 * Refresh cycles: (8192 refresh cycles /64ms) 7.8s maximum average periodic refresh interval * 2 variations of refresh Auto refresh Self refresh
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Document No. E0390E10 (Ver. 1.0) Date Published June 2003 (K) Japan URL: http://www.elpida.com
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This product became EOL in June, 2004.
Elpida Memory, Inc. 2003
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EBD25UC8AAFA-6B
Ordering Information
Data rate Mbps (max.) 333 Component JEDEC speed bin (CL-tRCD-tRP) Package DDR333B (2.5-3-3) 184-pin DIMM Contact pad Gold
Part number EBD25UC8AAFA-6B
Mounted devices M2S56D30ATP-60
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
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Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDD CK1 /CK1 VSS DQ10 DQ11 CKE0 VDD DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDD
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 47 48 49 50
Pin name NC A0 NC VSS NC BA1 DQ32 VDD DQ33
Pin No. 93 94 95 96 97 98 99 100 101
Pin name VSS DQ4 DQ5 VDD DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDD DQ12 DQ13 DM1/DQS10
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
Pin name VSS NC A10 NC VDD NC VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDD /CS0 NC DM5/DQS14
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
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DQS4 102 DQ34 103 VSS BA0 104 105 DQ35 106 DQ40 VDD /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 CK2 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122
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VDD 154 DQ14 155 DQ15 NC 156 157 VDD NC 158 159 DQ20 A12 VSS 160 161 162 DQ21 A11 163 164 DM2/DQS11 VDD 165 166 DQ22 A8 167 168
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VSS DQ46 DQ47 NC VDD DQ52 DQ53 NC VDD
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EBD25UC8AAFA-6B
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin name DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Pin No. 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name VDD DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name DQ23 VSS A6 DQ28 DQ29 VDD DM3/DQS12 A3 DQ30 VSS DQ31 NC NC VDD CK0 /CK0 Pin No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name DM6/DQS15 DQ54 DQ55 VDD NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDD SA0 SA1 SA2 VDDSPD
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VSS A1 NC 45 46 NC VDD
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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EBD25UC8AAFA-6B
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0 CKE0 Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag A0 to A12 A0 to A9
Bank select address
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CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC
DM0 to DM7/DQS9 to DQS16
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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No connection
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EBD25UC8AAFA-6B
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit3 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 Bit2 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 Bit1 Bit0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 Hex value 80H 08H 07H 0DH 0AH 01H 40H 00H 04H 60H 70H 00H 82H 08H 00H 01H 0EH 04H 0CH 01H 02H 20H C0H 75H 70H Comments 128 bytes 256 bytes DDR SDRAM 13 10 1 64 0 SSTL2 6.0ns*1 0.70ns*1 None. 7.6s x8 None. 1 CLK 2,4,8 4 2, 2.5 0 1 Differential Clock VDD 0.2V 7.5ns*1 0.70ns*1
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 to 26 27 28 29 30 31 32 33 34
Voltage interface level of this assembly 0 0 0 0 1 0 0 0 0 0 0 0 0
DDR SDRAM cycle time, CL = 2.5
SDRAM access from clock (tAC) DIMM configuration type Refresh rate/type
Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency
SDRAM module attributes
SDRAM device attributes: General Minimum clock cycle time at CL = 2
Maximum data access time (tAC) from 0 clock at CL = 2 0 Minimum row precharge time (tRP) Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) Module rank density 0 0 0 0 0
Address and command setup time 1 before clock (tIS) Address and command hold time after 1 clock (tIH) Data input setup time before clock 0 (tDS)
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
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1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1
00H 48H 18ns 12ns
30H
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48H 18ns 2AH 40H 42ns 256M bytes 80H 80H 45H 0.80ns*1 0.80ns*1 0.45ns*1
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EBD25UC8AAFA-6B
Byte No. 35 36 to 40 41 42 43 44 45 46 to 61 62 63
Function described Data input hold time after clock (tDH) Superset information Active command period (tRC) Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew Data hold skew (tQHS) Superset information SPD Revision Checksum for bytes 0 to 62
Bit7 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 0 0
Bit6 1 0 0 1 0 0 1 0 0 0 1 1 0 x 1 1 1 0 0 1 1
Bit5 Bit4 0 0 1 0 1 1 0 0 0 1 1 1 0 x 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 x 0 0 0 1 1 1 0
Bit3 0 0 1 1 1 1 0 0 0 0 1 1 0 x 0 0 0 0 0 0 0
Bit2 1 0 1 0 1 1 1 0 0 0 1 1 0 x 1 0 1 0 1 1 0 0 0 0 1 0 1
Bit1 Bit0 0 0 0 0 0 0 0 0 0 1 1 1 0 x 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 x 1 0 0 0 1 1 1 0 1 1 0 1 1
Hex value 45H 00H 3CH 48H 3CH 2DH 55H 00H 00H 22H 7FH FEH 00H xx 45H 42H 44H 32H 35H 55H 43H 38H 41H 41H 46H 41H 2DH
Comments 0.45ns*1 Future use 60ns*1 72ns*1 15ns*1 0.45ns*1 0.55ns*1 Future use
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64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 to 90 91 92 93 94 95 to 98 99 to 127 Revision code Revision code
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code
Continuation code Elpida Memory (ASCII-8bit code) E B D 2 5 U C 8 A A F A -- 6 B (Space) Initial (Space) Year code (HEX) Week code (HEX)
Manufacturer's JEDEC ID code Manufacturing location
Module part number Module part number
Module part number Module part number Module part number
Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number
Manufacturing date Manufacturing date Module serial number Manufacture specific data
Note: 1. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 x x 0 0 1 0 0 0 x x 1 0 1 1 0 1 0 0 0 1 0 0 1 1 1 0 0 0 x x x x x x
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1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 x x x x x x
36H 42H
20H 30H 20H xx xx
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EBD25UC8AAFA-6B
Block Diagram
/CS0 RS DQS0 8 DQ0 to DQ7 RS DQS1 8 DQ8 to DQ15 RS DQS2 8 DQ16 to DQ23 RS DQS3 8 DQ24 to DQ31 RS DQS4 8 DQ32 to DQ39 RS DQS5 8 DQ40 to DQ47 RS DQS6 8 RS RS RS DQS DQ /CS DM DQS DQ /CS DM RS DM7/DQS16 RS DQS DQ /CS DM RS DM6/DQS15 RS DQS DQ /CS DM RS DM5/DQS14 RS DQS DQ /CS DM RS DM4/DQS13 RS DQS DQ /CS DM RS DM3/DQS12 RS DQS DQ /CS DM RS DM2/DQS11 RS DQS DQ /CS DM RS DM1/DQS10 RS DM0/DQS9
U1
U11
U3
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VDD VREF VSS VDDID open Clock wiring Clock input CK0, /CK0 CK1, /CK1 CK2, /CK2
U13
U14
U6
* U1, U3, U6, U8, U11, U13, U14, U16 : 256M bits DDR SDRAM U20: 2k bits EEPROM RS: 22
Note: Wire per Clock loading table/Wiring diagrams.
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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DQ48 to DQ55 DQS7 8 DQ56 to DQ63 DDR SDRAMS 2DRAM loads 3DRAM loads 3DRAM loads
U16
U8
5.1 A0 to A12 (U1, U3, U6, U8, U11, U13, U14, U16) BA0, BA1 (U1, U3, U6, U8, U11, U13, U14, U16) /RAS (U1, U3, U6, U8, U11, U13, U14, U16) /CAS (U1, U3, U6, U8, U11, U13, U14, U16) /WE (U1, U3, U6, U8, U11, U13, U14, U16) CKE (U1, U3, U6, U8, U11, U13, U14, U16) 5.1 5.1 A0 to A12
Pr
BA0, BA1 /RAS /CAS /WE U1, U3, U6, U8, U11, U13, U14, U16 U1, U3, U6, U8, U11, U13, U14, U16 U1, U3, U6, U8, U11, U13, U14, U16 CKE0 SCL SCL A0
5.1 5.1
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Serial PD SDA SDA
U20
A1
A2
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
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EBD25UC8AAFA-6B
Logical Clock Net Structure
6DRAM loads DRAM1 5DRAM loads DRAM1
CLK DIMM connector
R = 120
DRAM2 DRAM3 DIMM connector DRAM4
R = 120
DRAM2 DRAM3
Capacitance DRAM5
/CLK DRAM5
DRAM6
DRAM6 3DRAM loads DRAM1
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4DRAM loads R = 120 DIMM connector
DRAM1
DRAM2 Capacitance DIMM connector Capacitance DRAM5
R = 120
Capacitance DRAM3
Capacitance DRAM5
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2DRAM loads R = 120 DIMM connector
Preliminary Data Sheet E0390E10 (Ver. 1.0)
DRAM6 1DRAM loads
Capacitance
DRAM1
Capacitance
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Capacitance Capacitance DIMM connector Capacitance DRAM5 Capacitance
R = 120
Capacitance DRAM3
Capacitance
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Capacitance
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EBD25UC8AAFA-6B
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Value -0.5 to +3.6 -0.5 to +3.6 50 8 0 to +70 -40 to +100 Unit V V mA W C C 1 Note
Notes: 1. DDR SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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Parameter Supply voltage Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs
DC Operating Conditions (TA = 0 to +70C) (DDR SDRAM Component Specification)
Symbol VDD,VDDQ VSS Min 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 Typ 2.5 0 0.50 x VDDQ VREF -- -- Max 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 Unit V V V V V V V 2 3 4 Notes 1
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VREF VTT VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC)
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-0.3 -- 0.5 x VDDQ - 0.2V 0.36 --
0.5 x VDDQ
0.5 x VDDQ + 0.2V V VDDQ + 0.6 V 5, 6
Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF - 0.18V if measurement.
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Preliminary Data Sheet E0390E10 (Ver. 1.0)
EBD25UC8AAFA-6B
DC Characteristics 1 (TA = 0 to +70C, VDD = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Floating idle Standby current Active power down standby current Active standby current Symbol IDD0 IDD1 IDD2P IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Grade max. 800 960 80 280 160 440 1520 1520 1200 24 2320 Unit mA mA mA mA mA mA mA mA mA mA mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 4, CL = 2.5, tRC = tRC (min.) CKE VIL Notes 1, 2, 9 1, 2, 5 4
CKE VIH, /CS VIH 4, 5 DQ, DQS, DM = VREF CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input VIL or VIH Input VDD - 0.2 V Input 0.2 V BL = 4 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
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Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current (4 banks interleaving)
5, 6, 7
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Symbol ILI ILO IOH IOL
Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9.
These IDD data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. 4 banks active. Only one bank is running at tRC = tRC (min.) The IDD data on this table are measured with regard to tCK = tCK (min.) in general. Command/Address transition once per one every two clock cycles.
DC Characteristics 2 (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current min. -16 -5 -16.8 16.8 max. 16 Unit A Test condition Notes
Note: 1. DDR SDRAM component specification.
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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5 -- --
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A mA mA
VDD VIN VSS
VDD VOUT VSS VOUT = VTT + 0.84V 1 1
VOUT = VTT - 0.84V
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EBD25UC8AAFA-6B
Pin Capacitance (TA = 25C, VDD = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE CK, /CK DQ, DQS max. 75 60 15 Unit pF pF pF Notes
AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V) (DDR SDRAM Componen Specification)
Parameter Symbol tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH tHZ tLZ tRPRE tRPST min. 7.5 6 0.45 0.45 min (tCH, tCL) -0.70 -0.60 -- tHP - 0.55 -0.70 -0.70 0.9 max 15 15 0.55 0.55 -- 0.70 0.60 0.45 -- 0.70 0.70 1.1 0.6 -- -- -- -- Unit ns ns tCK tCK tCK ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns 2 3 1 1 Notes
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Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS to DQ skew Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time Write preamble setup time Write preamble Write postamble DQS input high pulse width DQS input low pulse width Active to Read/Write delay
DQS output access time from CK, /CK
DQ/DQS output hold time from DQS
Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK
DQ and DM input pulse width
Write command to first DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK
Address and control input setup time Address and control input hold time Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period Auto refresh to Active/Auto refresh command period
Precharge to active command period
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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0.4 tDS 0.45 0.45 tDH tDIPW 1.75 tWPRES 0 tWPRE tWPST tDQSS tDSS 0.25 0.4 0.75 0.2 tDSH 0.2 tDQSH tDQSL tIS tIH tMRD tRAS tRC tRFC tRCD tRP 0.35 0.35 0.8 0.8 12 42 60 72 18 18
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-- 0.6 1.25 -- -- -- -- -- -- -- 120000 -- -- -- --
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6 ns 6 ns ns ns ns ns ns
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EBD25UC8AAFA-6B
Parameter Active to active command period Write recovery time Auto precharge write recovery and precharge time Internal write to Read command delay Exit self refresh to non-read command Exit self refresh to read command Exit power down to any non-read command Exit precharge power down to read command Average periodic refresh interval Symbol tRRD tWR tDAL tWTR tXSNR tXSRD tXPNR tXPRD tREF min. 12 15 35 1 75 200 1 1 -- max -- -- -- -- 7.8 Unit ns ns ns tCK ns tCK tCK tCK s 5 4 Notes
Notes: 1
2. 3.
4. 5. 6.
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic Low. If a previous write was in progress, DQS could be High, Low, or transitioning from High to Low at this time, depending on tDQSS. A maximum of eight auto refresh commands can be posted to any given DDR SDRAM device. tXPRD should be 200 tCK in the condition of the unstable CK operation during the power down mode. For command/address and CK and /CK slew rate 1.0V/ns.
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Preliminary Data Sheet E0390E10 (Ver. 1.0)
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EBD25UC8AAFA-6B
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
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Bank 0 Bank 1 Bank 2 Bank 3
[Bank Select Signal Table]
Remark: H: VIH. L: VIL.
CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ (input and output pins) Data are input to and output from these pins.
DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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L H L H
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BA0
BA1 L L
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H H
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EBD25UC8AAFA-6B
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins) 2.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected.
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Detailed Operation Part and Timing Waveforms
Refer to M2S56D20/30/40ATP datasheet.
Preliminary Data Sheet E0390E10 (Ver. 1.0)
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EBD25UC8AAFA-6B
Physical Outline
Unit: mm
3.18max (64.48) (DATUM -A-)
2.30
Component area (Front)
1 92 B 64.77 49.53 A
1.27 0.10
133.35
128.95
2 - 2.50
93
10.00
184
17.80
4.00 min
(Back)
4.00
R 2.00
3.00
Detail A
2.50 0.20
Detail B
1.27
(DATUM -A-) 2.175 R 0.90
6.62
0.20 0.15
6.35
3.80
1.00 0.05
1.80 0.10
ECA-TS2-0094-01
Preliminary Data Sheet E0390E10 (Ver. 1.0)
15
31.75
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EBD25UC8AAFA-6B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
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1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0390E10 (Ver. 1.0)
L
Pr
16
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CME0107
EBD25UC8AAFA-6B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
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Preliminary Data Sheet E0390E10 (Ver. 1.0)
L
Pr
17
M01E0107
od
t uc

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